The invention relates to structures and methods for decreasing the average instruction execution time for CISC (Complex Instruction Set Computer) type instructions in a pipelined architecture.
An approach to increasing computer system performance has been to design systems which execute so-called RISC (Reduced Instruction Set Computer) instruction sets rather than CISC (Complex Instruction Set Computer) instruction sets. In RISC instruction sets all instructions have the same length, and all use a so-called store-load architecture in which read and write operations from or to memory must be accomplished only with certain read and write instructions, whereas in CISC instruction sets it may be possible to include complex instructions that automatically effectuate certain read and write operations. Although RISC instruction sets at the present state of the art can be executed with Average Instruction Time (AIT) of only about 1.5 machine cycles per instruction, the "inflexibility" of RISC instruction sets often means that a much larger number of instructions must be included in a program to accomplish a particular task. In contrast, CISC instruction sets typically have an AIT of 10-15 machine cycles, but the number of CISC instructions required to accomplish a particular task may be far fewer than if RISC instructions are used. While each approach offers distinct advantages, at the present time it is unclear which approach will ultimately prevail. However, it is clear that it would be highly desirable if the AIT of executing CISC instructions could be substantially reduced, because the ease of programming with CISC instruction sets would be accompanied by the short AITs produced by RISC type architectures.
Pipelining techniques are well-known, wherein multiple stages of hardware, i.e., multiple pipelines, are provided so that each stage of the pipeline can be working on a different instruction at the same time, even though it may take as many machine cycles as there are stages in the pipeline to complete each instruction from start to finish. As long as the pipeline is kept full and operating smoothly, the AIT of each instruction will be much shorter than if pipelining techniques are not used. For CISC computer architectures, it has been impractical to have enough pipeline stages to shorten AITs of CISC instructions to much less than 10 machine cycles per instruction. In prior machines, the usual approach is to provide an instruction fetch pipeline which performs the functions of generating instruction addresses and loading the fetched instructions into an instruction buffer. The contents of the instruction buffer are read by an operand execution pipeline in which sequential microcode execution steps, each of which requires at least one machine cycle, are performed, resulting in typical AITs of 10-15 machines cycles for CISC type computers.